An integrated circuit (IC) performs logic functions through circuitry within the IC. Examples of such a circuit may include input/output (I/O) interfaces, storage buffers, processing units, etc. Each circuit has an associated function, e.g., a storage buffer, such as a memory element that stores information/data for later usage. A group of such circuitry that performs a function is known as Intellectual Property (IP) block.
Field Programmable Gate Arrays (FPGAs) are configured to perform a function through the implementation of IP blocks. Inserting configuration information into the FPGAs may define the IP block(s). The configuration data enables functionality of the FPGAs by configuring programmable logic elements. The IP blocks formed by way of the configuration data are also known as soft IP blocks.
The FPGA is known for its flexibility in inserting any type of soft IP blocks. The FPGA can be programmed from one soft IP block to another. As such, FPGA companies may not be able to control types of IP blocks the FPGA may support. Furthermore, soft IP blocks may be propriety designs of FPGA companies or of a third party design house and these entities may desire to protect the soft IP blocks from unauthorized use.
It is within this context that the embodiments described herein arise.